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NB6L239 2.5 V / 3.3 V Any Differential Clock IN to Differential LVPECL OUT /1/2/4/8, /2/4/8/16 Clock Divider
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The NB6L239 is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider circuits drive a pair of differential LVPECL outputs. (More device information on page 7). * Maximum Clock Input Frequency, 3.0 GHz * Input Compatibility with LVDS/LVPECL/CML/HSTL * Rise/Fall Time 70 ps Typical * < 10 ps Typical Output-to-Output Skew * Ex. 622 MHz Input Generates 38.8 MHz to 622 MHz Outputs * Internal 50 W Termination Provided * Random Clock Jitter < 1 ps RMS * Divide-by-1 Edge of QA Aligned to QB Divided Output * Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V * Master Reset for Synchronization of Multiple Chips * VBBAC Reference Output * Synchronous Output Enable/Disable
MARKING DIAGRAM*
Bottom View QFN-16 MN SUFFIX CASE 485G XXXX A L Y W
XXXX XXXX ALYW
= Device Code = Assembly Location = Wafer Lot = Year = Work Week
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 11 of this data sheet.
SELA0 SELA1 QA QA
CLK VT CLK
QB QB EN SELB0 SELB1 MR
+
Figure 1. Simplified Logic Diagram
(c) Semiconductor Components Industries, LLC, 2004
1
April, 2004 - Rev. 0
Publication Order Number: NB6L239/D
NB6L239
MR 16 1 2 NB6L239 CLK VBBAC 3 4 5 EN 6 7 8 10 9 QB QB SELA0 SELA1 VCC 15 14 13 12 11
VT CLK
QA QA
SELB0 SELB1 VEE Exposed Pad (EP)
Figure 2. Pinout: QFN-16 (Top View)
Table 1. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name VT CLK CLK VBBAC EN* SELB0* SELB1* VEE QB QB QA QA VCC SELA1* SELA0* MR** EP LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply LVPECL Output LVPECL Output LVPECL Output LVPECL Output Power Supply LVCMOS/LVTTL Input LVCMOS/LVTTL Input LVCMOS/LVTTL Input Power Supply (OPT) LVPECL, CML, LVDS, HSTL Input LVPECL, CML, LVDS, HSTL Input I/O Description Internal 100 W Center-Tapped Termination Pin for CLK and CLK. Noninverted Differential CLOCK Input. Inverted Differential CLOCK Input. Output Voltage Reference for Capacitor Coupled Inputs, Only. Synchronous Output Enable Clock Divide Select Pin Clock Divide Select Pin Negative Supply Voltage Inverted Differential Output. Typically terminated with 50 W resistor to VTT. Noninverted Differential Output. Typically terminated with 50 W resistor to VTT. Inverted Differential Output. Typically terminated with 50 W resistor to VTT. Noninverted Differential Output. Typically terminated with 50 W resistor to VTT. Positive Supply Voltage. Clock Divide Select Pin Clock Divide Select Pin Master Reset Asynchronous, Default Open High, Asserted LOW The Exposed Pad on the QFN-16 package bottom is thermally connected to the die for improved heat transfer out of package. The pad is not electrically connected to the die, but is recommended to be electrically and thermally connected to VEE on the PC board.
*Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN.
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NB6L239
+
SELA0 VCC SELA1 B1 B2 B4 R B8 QA QA
A CLK VT CLK 50 W 50 W
R B2 B4 B EN SELB0 B8 B16
QB QB
SELB1 MR VBBAC
+
VEE
Figure 3. Logic Diagram Table 2. FUNCTION TABLES
CLK EN* L H X MR** H H L FUNCTION Divide Hold Q Reset Q
X
Table 3. CLOCK DIVIDE SELECT, QA OUTPUTS
SELA1* L L H H SELA0* L H L H QA Outputs Divide by 1 Divide by 2 Divide by 4 Divide by 8
Table 4. CLOCK DIVIDE SELECT, QB OUTPUTS
SELB1* L L H H SELB0* L H L H QB Outputs Divide by 2 Divide by 4 Divide by 8 Divide by 16
= Low-to-High Transition = High-to-Low Transition X = Don't Care *Pins will default LOW when left OPEN. **Pins will default HIGH when left OPEN.
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NB6L239
Table 5. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 75 kW > 1500 V > 150 V > 1000 V Level 1 UL 94 V-0 @ 0.125 in 367
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Oxygen Index: 28 to 34
1. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.
MAXIMUM RATINGS
Symbol VCC VI Iout IBB TA Tstg qJA qJC Tsol Parameter Positive Mode Power Supply Input Voltage Output Current VBBAC Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm Standard Board < 3 sec @ 248C Condition 1 VEE = 0 V VEE = 0 V Continuous Surge VEE v VI v VCC Condition 2 Rating 3.6 3.6 50 100 0.5 -40 to +85 -65 to +150 41.6 35.2 4.0 265 Units V V mA mA mA C C C/W C/W C/W C
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
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NB6L239
Table 6. DC CHARACTERISTICS, CLOCK INPUTS, LVPECL OUTPUTS
(VCC = 2.375 V to 3.465 V, VEE = 0 V)
-405C Symbol IEE VOH Characteristic Power Supply Current Output HIGH Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V Output LOW Voltage (Notes 2, 3) VCC = 3.3 V VCC = 2.5 V Min 30 VCC-1150 2150 1350 VCC-1870 1430 630 Typ 40 VCC-1060 2240 1440 VCC-1760 1540 740 Max 50 VCC-950 2350 1550 VCC-1630 1670 870 Min 30 VCC-1100 2200 1400 VCC-1820 1480 680 255C Typ 40 VCC-1015 2285 1485 VCC-1700 1600 800 Max 50 VCC - 900 2400 1600 VCC-1580 1720 920 Min 30 VCC-1050 2250 1450 VCC-1770 1530 730 85C Typ 40 VCC -980 2320 1520 VCC-1660 1640 840 Max 50 VCC - 850 2450 1650 VCC-1530 1770 970 mV Unit mA mV
VOL
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (Figures 7, 10) Vth Input Threshold Reference Voltage (Note 4) Single-ended Input HIGH Voltage Single-ended Input LOW Voltage Output Voltage Reference @ 100 mA (Note 7) VCC = 3.3 V VCC = 2.5 V 100 VCC - 100 100 VCC - 100 100 VCC - 100 mV
VIH VIL VBBAC
Vth + 100 VEE VCC-1460 1840 1040 VCC-1330 1970 1170
VCC Vth - 100 VCC-1200 2100 1300
Vth + 100 VEE VCC-1460 1840 1040 VCC-1340 1960 1160
VCC Vth - 100 VCC-1200 2100 1300
Vth + 100 VEE VCC-1460 1840 1040 VCC-1350 1950 1150
VCC Vth - 100 VCC-1200 2100 1300
mV mV mV
DIFFERENTIAL INPUT DRIVEN DIFFERENTIALLY (Figures 8, 9, 11) (Note 6) VIHD VILD VCMR Differential Input HIGH Voltage Differential Input LOW Voltage Input Common Mode Range (Differential Cross-point Voltage) (Note 5) Differential Input Voltage (VIHD(CLK) - VILD(CLK)) and (VIHD(CLK)-VILD(CLK)) Internal Input Termination Resistor 100 VEE 50 VCC VCC - 100 VCC - 50 100 VEE 50 VCC VCC - 100 VCC - 50 100 VEE 50 VCC VCC - 100 VCC - 50 mV mV mV
VID
100
VCC - VEE
100
VCC - VEE
100
VCC - VEE
mV
RTIN
45
50
55
45
50
55
45
50
55
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. Input and output parameters vary 1:1 with VCC. 3. Outputs loaded with 50 W to VCC - 2.0 V for proper operation. 4. Vth is applied to the complementary input when operating in single-ended mode. 5. VCMRMIN varies 1:1 with VEE, VCMRMAX varies 1:1 with VCC. 6. Input and output voltage swing is a single-ended measurement operating in differential mode. 7. VBBAC used to rebias capacitor-coupled inputs only (see Figures 16 and 17).
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NB6L239
Table 7. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = -40C to +85C)
Symbol VIH VIL IIH IIL Characteristic Input HIGH Voltage (LVCMOS/LVTTL) Input LOW Voltage (LVCMOS/LVTTL) Input HIGH Current Input LOW Current Min 2.0 VEE -150 -150 Typ Max VCC 0.8 150 150 Unit V V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 8)
-40C Symbol fin VOUTPP Characteristic Maximum Input CLOCK Frequency Output Voltage Amplitude (Notes 10, 11) QA(B2, 4, 8), QB(Bn) fin v 3.0 GHz QA(B1), QB(Bn) fin v 2.5 GHz QA(B1), QB(Bn) 2.5 GHz < fin v 3.0 GHz Propagation Delay to Output Differential @ 50 MHz Reset Recovery Setup Time @ 50 MHz Hold Time @ 50 MHz Within-Device Skew @ 50 MHz Device-to-Device Skew Duty Cycle Skew Minimum Pulse Width RMS Random Clock Jitter (See Figure 20. Fmax/JITTER) Input Voltage Swing (Differential Configuration) (Note 10) Output Rise/Fall Times @ 50 MHz (20% - 80%) Qn, Qn 100 30 60 EN, CLK SELA/B, CLK CLK, EN CLK, SELA/B (Note 9) (Note 9) (Note 9) MR 550 <1 VCC -VEE 120 100 30 65 CLK, Qn MR, Qn 450 450 300 370 330 0 0 0 150 700 650 650 650 470 370 -90 -60 -300 65 200 5 25 25 30 80 40 550 <1 VCC -VEE 120 100 30 70 570 430 Min Typ Max 3.0 450 450 250 370 330 0 0 0 150 700 650 630 650 470 380 -90 -60 -300 65 200 5 30 30 30 90 45 550 <1 VCC -VEE 120 570 430 Min 25C Typ Max 3.0 450 450 200 400 330 0 0 0 150 700 650 610 650 500 400 -90 -60 -300 65 200 6 30 30 35 90 45 600 480 ps ps ps ps ps Min 85C Typ Max 3.0 Unit GHz mV
tPLH, tPHL tRR ts th tskew
tPW tJITTER VINPP tr tf
ps ps mV ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 8. Measured using a 750 mV, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 9. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 10. Input and output voltage swing is a single-ended measurement operating in differential mode. 11. Output Voltage Amplitude (VOHCLK - VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency divided by n, fout = fin B n. Input CLOCK frequency is v3.0 GHz.
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NB6L239
Application Information single-ended input CLOCK signals. For the The NB6L239 is a high-speed, low skew clock divider capacitor-coupled CLK and/or CLK inputs, VBBAC should with two divider circuits, each having selectable clock divide ratios; B1/2/4/8 and B2/4/8/16. Both divider be connected to the VT pin and bypassed to ground with a circuits drive a pair of differential LVPECL outputs. The 0.01 mF capacitor. Inputs CLK and CLK must be signal internal dividers are synchronous to each other. Therefore, driven or auto oscillation may result. the common output edges are precisely aligned. The common enable (EN) is synchronous so that the The NB6L239 clock inputs can be driven by a variety of internal divider flip-flops will only be enabled/disabled differential signal level technologies including LVDS, when the internal clock is in the LOW state. This avoids any LVPECL, HSTL, or CML. The differential clock input chance of generating a runt pulse on the internal clock when buffer employs a pair of internal 50 W termination resistors the device is enabled/disabled, as can happen with an in a 100 W center-tapped configuration and accessible via asynchronous control. The internal enable flip-flop is the VT pin. This feature provides transmission line clocked on the falling edge of the input clock. Therefore, all termination on-chip, at the receiver end, eliminating associated specification limits are referenced to the negative external components. The VBBAC reference output can be edge of the clock input. used to rebias capacitor-coupled differential or
MR
CLK Q (/1) Q (/2) Q (/4) Q (/8) Q (/16)
Figure 4. Timing Diagram
CLK tRR MR tRR
Q (/n)
Figure 5. Master Reset Timing Diagram
NOTE: On the rising edge of MR, Q goes HIGH after the first rising edge of CLK. Internal Clock Disabled CLK Q (/n) Internal Clock Enabled
EN
Figure 6. Output Enable Timing Diagrams
The EN signal will "freeze" the internal divider flip-flops on the first falling edge of CLK after its assertion. The internal divider flip-flops will maintain their state during the freeze. When EN is deasserted (LOW), and after the next falling edge of CLK, then the internal divider flip-flops will "unfreeze" and continue to their next state count with proper phase relationships.
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NB6L239
CLK VIH VIL Vth CLK CLK Vth CLK
Figure 8. Differential Inputs Driven Differentially
Figure 7. Differential Input Driven Single-Ended
CLK CLK VID = |VIHD(CLK) - VILD(CLK)| VIHD VILD
Figure 9. Differential Inputs Driven Differentially
VCC Vthmax CLK Vth
VIHmax VILmax
VCC VCMmax
VIHDmax VILDmax
VCMR
Vthmin VEE CLK
VIHmin VILmin
VCMmin VEE
VIHDmin VILDmin
Figure 10. Vth Diagram
Figure 11. VCMR Diagram
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NB6L239
VCC VCC VCC VCC
Zo = 50 W LVPECL Driver VT = VCC - 2.0 V
NB6L239 CLK 50 W 50 W LVDS Driver
Zo = 50 W
NB6L239 CLK 50 W
VT = OPEN 50 W Zo = 50 W CLK
Zo = 50 W
CLK
VEE
VEE
VEE
VEE
Figure 12. LVPECL Interface
Figure 13. LVDS Interface
VCC
VCC
VCC
VCC
Zo = 50 W CML Driver
NB6L239 CLK 50 W HSTL Driver
Zo = 50 W
NB6L239 CLK 50 W
VT = VCC 50 W Zo = 50 W CLK
VT =VEE 50 W Zo = 50 W CLK
VEE
VEE
VEE
VEE
Figure 14. Standard 50 W Load CML Interface
Figure 15. Standard 50 W Load HSTL Interface
VCC
VCC
VCC
VCC
Zo = 50 W Differential Driver
NB6L239 CLK 50 W Single-Ended Driver
Zo = 50 W
NB6L239 CLK 50 W
VT = VBBAC* 50 W Zo = 50 W CLK
VT = VBBAC* 50 W CLK
VEE
VEE
VEE
VEE
Figure 16. Capacitor-Coupled Differential Interface (VT Connected to VBBAC)
*VBBAC bypassed to ground with a 0.01 mF capacitor.
Figure 17. Capacitor-Coupled Single-Ended Interface (VT Connected to VBBAC)
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NB6L239
VOUTPP, OUTPUT VOLTAGE AMPLITUDE (mV) (TYPICAL) 800 700 600 500 400 300 200 100 0 8 7 6 5 4 3 2 1 0
0
1
2
3
fout, CLOCK OUTPUT FREQUENCY (GHz)
Figure 18. Output Voltage Amplitude (VOUTPP)/RMS Jitter versus Clock Output Frequency at Ambient Temperature (Typical) (fout = fin B n).
CLK VINPP = VIH(CLK) - VIL(CLK) CLK Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 19. AC Reference Measurement
NB6L239 Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 20. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
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JITTEROUT ps (RMS)
EEEEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEEEE
NB6L239
ORDERING INFORMATION
Device NB6L239MN NB6L239MNR2 Package QFN-16 QFN-16 Shipping 123 Units / Rail 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPS I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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NB6L239
PACKAGE DIMENSIONS
QFN-16 CASE 485G-01 ISSUE A
-X- A M -Y-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION D APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN MAX 3.00 BSC 3.00 BSC 0.80 1.00 0.23 0.28 1.75 1.85 1.75 1.85 0.50 BSC 0.875 0.925 0.20 REF 0.00 0.05 0.35 0.45 1.50 BSC 1.50 BSC 0.875 0.925 0.60 0.80 INCHES MIN MAX 0.118 BSC 0.118 BSC 0.031 0.039 0.009 0.011 0.069 0.073 0.069 0.073 0.020 BSC 0.034 0.036 0.008 REF 0.000 0.002 0.014 0.018 0.059 BSC 0.059 BSC 0.034 0.036 0.024 0.031
B N 0.25 (0.010) T 0.25 (0.010) T J R 0.08 (0.003) T E H G
5 8
DIM A B C D E F G H J K L M N P R
C K -T-
SEATING PLANE
L
4
9
F
1 12
16
13
P
D
NOTE 3 M
0.10 (0.004)
TXY
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NB6L239/D

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